ASIC Engineer I, Annapurna Labs, Early Career - 2027

What you'll do

• Design and implement RTL; develop and run verification to validate functionality and coverage.
• Support synthesis, timing analysis, and physical-design flows; debug design issues through simulation and analysis.
• Collaborate across chip-development teams and document and present design decisions.

What they ask for

• Bachelor's or Master's degree program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with final graduation date of May 2027 or earlier.
• Coursework or project experience in digital logic design and computer architecture.
• Familiarity with a hardware description language: Verilog, SystemVerilog, or VHDL.
• Understanding of combinational and sequential logic, finite state machines, timing, and clocking.

Nice to have

• Degree focus in VLSI, digital design, or computer architecture; experience with industry-standard EDA tools (Cadence, Synopsys, or equivalent).
• Scripting experience (Python, Perl, TCL, or shell) for automation and design flows; prior internship, research, or lab experience in chip design, embedded systems, or hardware development.

Pay

116,100.00 USD Annually (base salary); 133,600.00 USD Annually (base salary)

Tools

Verilog, SystemVerilog, VHDL, Cadence, Synopsys, Python, Perl, TCL

AI focus

May involve designing or verifying ASICs for machine learning accelerators (Trainium/Inferentia).