ASIC III - AMZ27336.4

What you'll do

• Define, design, and validate next-generation ML chips, cards, and server integration; contribute to HBM, memory, and SerDes design and execution.
• Lead IP integration and 2.5D design, bring-up, characterization, and validation, including post-silicon IO and HBM/DDR stack bring-up.
• Debug system-level functional and performance issues, work with vendors, and collaborate across architecture, design, and software teams.

What they ask for

• Master’s degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering, or a related field, plus 5 years of experience in the job offered or a related occupation; alternatively, a relevant bachelor’s degree or foreign equivalent plus 7 years of progressively responsible post-baccalaureate experience.
• 3 years of experience with SOC/IO/Subsystems.
• 3 years of experience with DDR/HBM PHY and controller topics, including training, timing parameters, or controller features.
• 3 years of experience in each of the other listed areas: IP integration and silicon/2.5D packaging; physical-design support and clocking/timing constraints; cross-functional triage; post-silicon bring-up; boot/reset/training definition; system debug through production; and work with third-party IP and memory vendors.

Pay

$202779 - $215300 (base salary)

Tools

HBM, DDR, Serdes, SOC/IO/Subsystems, 2.5D

AI focus

Design and validation of next-generation AWS machine-learning chips, cards, and server integration.