MLA Design Verification Engineer I, Annapurna Labs

What you'll do

• Verify and validate that hardware and software solutions meet their intended functionality.
• Develop and execute verification and validation plans.
• Measure team progress against customer metrics.

What they ask for

• Currently has or is pursuing a Bachelor's degree or above in Electrical Engineering, Computer Engineering, or a related field.
• 1+ years of design verification experience using System Verilog and UVM.
• 1+ years of testbench development experience, including stimulus, checkers, assertions, and coverage.

Nice to have

• Experience with C/C++ and Object-Oriented Programming.
• Experience verifying multiple logic levels, from IP blocks to SoCs to full system testing.

Pay

116,100.00 USD Annually (base salary)

Tools

System Verilog, UVM, C/C++

AI focus

Hardware verification for machine-learning acceleration, including AWS Inferentia.