Principal Technical Program Manager

What you'll do

• Manage integrated schedules, critical paths, dependencies, and schedule impacts across tape-outs, engineering samples, and production ramp.
• Coordinate weekly program status and drive responses to verification convergence, design-partner, infrastructure, and IP-delivery risks.
• Manage external partner schedules and infrastructure readiness, escalating delivery gaps before they affect tape-out.

What they ask for

• 10+ years of hands-on work managing complex technology projects.
• 10+ years working directly with engineering teams.
• Deep working knowledge of the chip development lifecycle, including RTL verification milestones, physical design convergence, DFT, and timing closure.
• Experience managing programs with external design partners and IP vendors; ability to build dependency-based integrated schedules and communicate status to VP-level audiences.

Nice to have

• Experience with multi-die, chiplet, or advanced packaging programs; HBM integration, die-to-die interfaces, high-speed serial subsystems, or leading-edge foundry nodes.
• Background in ML accelerator or high-performance compute silicon, or infrastructure capacity planning for large-scale chip development programs.

Pay

203,500.00 - 275,300.00 USD annually (base salary); 177,000.00 - 239,400.00 USD annually (base salary)

Tools

RTL, DFT, HBM, Trainium, Inferentia, EDA

AI focus

The role manages execution of ML accelerator silicon programs, including chips that power machine-learning infrastructure; it does not specify developing AI models or algorithms.