Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

What you'll do

• Develop methodologies and infrastructure that help design teams work efficiently while maintaining quality.
• Build and enhance design flows to increase team productivity.
• Work with vendors to evaluate and qualify design tools and updated versions.

What they ask for

• 7+ years of ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller).
• 7+ years of digital design in communication systems, full-custom analog or RF layout, wireless communications systems and implementation, and verification in communication systems.
• 8+ years creating and maintaining automation frameworks for Post-Silicon Flow.
• 5+ years of UVM, C, System C, and scripting experience.

Nice to have

• Master's degree or Ph.D. in Electrical Engineering or a related field.
• Experience in RTL coding and debug; performance, power, and area analysis and trade-offs; modern ASIC/FPGA design and verification tools; or SOC bring-up and post-silicon validation.

Pay

USD 213,000.00 - 287,500.00 annually (base salary); USD 185,200.00 - 250,000.00 annually (base salary)

Tools

ASIC, STA, UVM, C, System C, RTL, ASIC/FPGA, SOC

AI focus

The role supports silicon development for machine-learning acceleration and AI workloads; no specific AI development duties are stated.