Amazon
Senior FPGA Engineer, LEO Payload FPGA
$185K–$288K
Sunnyvale, CA +2 · Senior · Full-time · Posted Jun 3, 2026
- Location
- Sunnyvale, CA
Redmond, WA
NORTHRIDGE, CA - Experience
- 7+ years in FPGA design and implementation using System Verilog.
- Education
- Bachelor's degree in Electrical Engineering or a related field.
- Visa sponsorship
- Candidates must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
About the job
Design, implement, validate, and support FPGA solutions for networking and satellite communications functions in Amazon’s LEO broadband system.
What you'll do
- Own FPGA bitstreams through architecture, RTL design, implementation, timing closure, simulation, and laboratory validation.
- Collaborate with systems, communications, networking, hardware, firmware, and software teams to develop and test FPGA-based functions and prototypes.
- Analyze design trade-offs to optimize customer experience and technology resources for cost, size, power, performance, and features.
What they ask for
- Bachelor's degree in Electrical Engineering or a related field.
- Experience with modern ASIC/FPGA design and verification tools and writing test scripts to validate FPGA images in hardware.
- 7+ years experience in FPGA design and Implementation using System Verilog.
- Experience with Xilinx/AMD (or Altera) FPGAs and uArchitecture, RTL coding, FPGA timing and power optimization, simulation, and validation.
Nice to have
- Experience developing Python tests for hardware testing and Cocotb simulation environments.
- Experience with high-speed networking, SerDes, 50G/100G Ethernet or Interlaken; familiarity with AXI4 and AXI Streaming interfaces; or a track record supporting FPGA and ASIC products.
Pay
USD 185,200.00 - 250,000.00 annually (base salary); USD 213,000.00 - 287,500.00 annually (base salary); USD 185,200.00 - 250,000.00 annually (base salary)
Tools
System Verilog, Python, Xilinx/AMD, Altera, Cocotb, SerDes, 50G/100G Ethernet, AXI4
Model-written summary · the original posting is authoritative