Amazon
Senior FPGA Engineer, Payload Hardware Development, Leo PAA Hardware
$159K–$215K
Redmond, WA · Senior · Full-time · Posted Aug 19, 2026
- Experience
- 10+ years with a bachelor’s degree; 7+ years with Verilog and/or SystemVerilog and FPGA design tools; 7+ years with simulation tools; 5+ years with UVM. Preferred: 7+ years with a master’s or Ph.D.
- Education
- Bachelor’s degree in Electrical Engineering or a related field. Preferred: Master’s or Ph.D. degree in Electrical Engineering or a related field.
- Visa sponsorship
- Candidates must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
About the job
Develop and validate FPGA-based digital networking and communications designs for Amazon’s low Earth orbit satellite broadband system, from architecture through production and hardware integration.
What you'll do
- Own FPGA bitstreams and take designs through RTL, physical implementation, timing closure, simulation, and lab validation.
- Design, implement, verify, debug, and optimize FPGA architectures and networking functions; support hardware integration and production.
- Collaborate with systems, hardware, firmware, and software teams on architecture, prototypes, system bring-up, and design trade-offs.
What they ask for
- Bachelor’s degree in Electrical Engineering or related field with 10+ years of experience.
- 7+ years with Verilog and/or SystemVerilog for RTL design and verification, and FPGA design tools such as Vivado or Libero SoC (or equivalent).
- 7+ years with simulation tools such as ModelSim or Vivado Simulator (or equivalent), and 5+ years with UVM (SystemVerilog and/or SystemC).
- Experience with high-speed interfaces (PCIe, DDR, Ethernet, SerDes) and serial protocols (SPI, I2C, I3C, UART).
Nice to have
- Master’s or Ph.D. in Electrical Engineering or related field with 7+ years of experience.
- Experience with Versal ACAP or IGLOO2, volume production, power islands and power gating, SoC bring-up, post-silicon validation, or signal processing and communications.
Pay
159,200.00 - 215,300.00 USD annually (base salary)
Tools
Verilog HDL, SystemVerilog, Vivado, Libero SoC, ModelSim, Vivado Simulator, UVM, SystemC
Model-written summary · the original posting is authoritative