Amazon
SOC Top Level Physical Design Engineer, Annapurna Labs
$185K–$288K
Austin, TX +2 · Full-time · Posted May 11, 2026
- Location
- Austin, TX
San Diego, CA
Cupertino, CA - Experience
- BS + 10yrs or MS + 7yrs; 5+ years in physical verification for advanced technology nodes.
- Education
- BS or MS in EE/CS or a related field.
About the job
Leads physical design verification and integration for custom machine-learning SoCs, from floorplanning through signoff and tapeout.
What you'll do
- Drive full-chip floorplan, placement, integration, physical verification signoff, and tapeout.
- Develop and optimize physical verification methodologies; perform DRC, LVS, and PERC checks and resolve issues with design and layout teams.
- Coordinate with foundries and mentor junior engineers on verification and closure.
What they ask for
- Scripting experience with Python, Perl, Bash, or PowerShell.
- BS + 10yrs or MS + 7yrs in EE/CS or a related field; 5+ years in physical verification for advanced technology nodes.
- Knowledge of backend physical design flows for chip-top/subsystems (FC/Innovus) and expert knowledge of physical verification tools (Calibre, IC Validator, PVS).
- Strong understanding of semiconductor manufacturing processes and design rules, proven successful tape-outs, and strong communication and collaboration abilities.
Nice to have
- Mentoring, leading, or managing junior engineers; integration and verification experience in advanced nodes (5nm or below).
- Knowledge of custom and digital design flows, DFM, reliability verification, physical design across technologies such as DDR, PCIe, and fabrics, or QOR metrics and trend analysis.
Pay
USD 213,000.00 - 287,500.00 annually (base salary); USD 185,200.00 - 250,000.00 annually (base salary)
Tools
Python, Perl, Bash, PowerShell, FC, Innovus, Calibre, IC Validator
AI focus
Supports physical design of AWS Inferentia and Trainium machine-learning systems; no AI development work is stated.
Model-written summary · the original posting is authoritative