Amazon
Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
$213K–$288K
Cupertino, CA · Senior · Full-time · Posted Mar 16, 2026
- Experience
- 5+ years in RTL design for SOC; 5+ years in VLSI engineering; 5+ years with code quality tools. Preferred: 5+ years of practical semiconductor design work including full-chip and subsystem integration experience.
- Education
- Bachelor's degree in Electrical Engineering or a related field; preferred Master's degree in electrical engineering, computer engineering, or equivalent.
About the job
Design and integrate efficient RTL for AWS machine-learning accelerator SoCs, including analysis and quality checks to meet performance, power, and area targets.
What you'll do
- Develop SystemVerilog RTL and microarchitecture; deliver synthesis- and timing-clean designs with constraints.
- Integrate subsystems into top-level SoCs and verify clock, reset, functional, and DFT signal routing.
- Analyze designs and make feature, power, performance, and area trade-offs; perform lint and clock-domain-crossing checks.
What they ask for
- Bachelor's degree in Electrical Engineering or a related field.
- 5+ years in RTL design for SOC.
- 5+ years in VLSI engineering.
- 5+ years with code quality tools including Spyglass, LINT, or CDC.
Nice to have
- Master's degree in electrical engineering, computer engineering, or equivalent.
- Experience with RTL coding and debug, PPA analysis, Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints, Python, data path design, interconnects, or AXI protocol.
Pay
213,000.00 - 287,500.00 USD annually (base salary)
Tools
SystemVerilog RTL, Spyglass, LINT, CDC, Python, Assertions, SDC constraints, AXI protocol
AI focus
Design and optimize ASIC hardware for AWS machine-learning acceleration, including AWS Inferentia inference servers.
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