Amazon
Sr. Formal Verification Engineer, Amazon Leo
$185K–$288K
Austin, TX +3 · Senior · Full-time · Posted Aug 26, 2026
- Location
- Austin, TX
Sunnyvale, CA
Redmond, WA
San Diego, CA - Experience
- 8+ years of ASIC/SoC design verification with a strong focus on formal verification.
- Education
- Bachelor's degree in electrical engineering, computer engineering, or equivalent
- Visa sponsorship
- Candidates must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
About the job
Leads formal verification for modem SoCs, proving design correctness, finding corner-case bugs, and improving verification methods across teams.
What you'll do
- Develop formal strategies, properties, proof-convergence methods, reusable infrastructure, and automated regression flows.
- Collaborate with design and verification teams to integrate formal methods with simulation and emulation, and drive coverage closure.
- Mentor engineers and evaluate formal verification tools with EDA vendors.
What they ask for
- Bachelor's degree in electrical engineering, computer engineering, or equivalent.
- 8+ years of ASIC/SoC design verification experience with a strong focus on formal verification.
- Experience with JasperGold and/or Questa Formal; strong SystemVerilog Assertions (SVA) and formal property specification skills.
- Experience with formal verification applications and proof convergence; proficiency in SystemVerilog, UVM concepts, and AI/LLM tools for formal verification workflows.
Nice to have
- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field focused on formal methods.
- Experience with complex SoCs, modem/PHY/DSP or satellite communications, scripting, CI workflows, or emulation-based verification.
Pay
USD 185,200.00 - 250,000.00 annually base salary; USD 213,000.00 - 287,500.00 annually base salary; USD 185,200.00 - 250,000.00 annually base salary; USD 185,200.00 - 250,000.00 annually base salary
Tools
JasperGold, Questa Formal, SystemVerilog Assertions (SVA), SystemVerilog, UVM, Python, TCL, Perl
AI focus
Use AI/LLM tools to accelerate formal verification, including AI-assisted SVA generation, property debugging, proof exploration, and automated constraint refinement.
Model-written summary · the original posting is authoritative