Drimva

Amazon

Sr Hardware Development Engineer, CPU and Memory Performance Team

$159K–$215K

Seattle, WA +1 · Senior · Full-time · Posted May 27, 2026

Location
Seattle, WA
Portland, OR
Experience
5+ years in each of the three experience areas listed in the basic qualifications; preferred experience includes 5+ years in several specified areas.
Education
Bachelor’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering or related discipline; preferred Master's degree in electrical engineering, computer engineering, or equivalent.

About the job

Leads AWS server memory engineering, driving the memory roadmap and delivering memory solutions that meet quality and performance needs at scale.

What you'll do

  • Drive AWS’s memory roadmap and ensure memory solutions meet quality and performance requirements.
  • Design, develop, validate, launch, monitor, and troubleshoot memory solutions with internal and external engineering teams.
  • Support debugging and root-cause analysis of memory failures and hardware and software issues in large-scale systems.

What they ask for

  • Bachelor’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related discipline.
  • 5+ year of experience with customer support for successive debugging and root-causing memory failures.
  • 5+ years of experience in memory, memory subsystem design.
  • 5+ years of experience identifying and root-causing hardware and software issues in large scale systems.

Nice to have

  • Master's degree in electrical engineering, computer engineering, or equivalent.
  • Experience with new memory technology bring up, statistical analysis using large scale data, or memory standardization and related areas including JEDEC, CPU architecture, RAS, DDR Memory technology, system performance, security, and troubleshooting.

Pay

159,200.00 - 215,300.00 USD annually (base salary)

Tools

JEDEC, CPU architecture, RAS, DDR Memory technology

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 4, 2026 (UTC)