Sr. Manager, Foundation IP (Standard Cells & Memories),, Annapurna Labs

What you'll do

• Own foundation IP roadmaps, vendor and foundry engagement, and IP quality and release processes.
• Lead PPA evaluation, memory and custom-cell development, characterization, and integration into silicon design flows.
• Manage and develop a team of engineers and report IP health, risks, and PPA results to senior leadership.

What they ask for

• 3+ years of people management experience managing engineers.
• BS in Electrical or Computer Engineering with 12+ years, MS with 10+ years, or PhD with 7+ years of experience in standard cell, memory, or custom digital circuit design.
• Hands-on transistor-level design across standard cells, sequentials/latches, and SRAM or register files in FinFET or GAA technologies at 5nm or below.
• Experience interfacing with foundation IP vendors or foundries; evaluating library and memory PPA; characterization and EDA views; custom design and verification tools; and scripting in Python, Tcl, Perl, or SKILL.

Nice to have

• Experience on N3, N2 or below, including backside power delivery and mixed-height standard cell libraries.
• Experience with latch-based arrays, custom multi-port register files, TCAM/CAM, or custom and combo cells for high-performance processors or ML accelerators.

Pay

277,400.00 - 350,000.00 USD annually (base salary); 241,200.00 - 325,600.00 USD annually (base salary)

Tools

Synopsys Fusion Compiler, Cadence Innovus, Synopsys PrimeLib/SiliconSmart, Cadence Liberate, Cadence Virtuoso, Synopsys Custom Compiler, Python, Tcl

AI focus

Develops and enables foundation IP for Trainium and Inferentia AI accelerator SoCs, including memories and standard cells optimized for ML workloads.