Sr MLA Design Verification Engineer, Cloud-Scale Machine Learning Acceleration - Annapurna Labs

What you'll do

• Verify custom chip designs at the SOC level, integrating third-party IPs and VIPs into the SOC testbench.
• Create test plans, random test cases, and coverage plans; maintain smoke tests and regression infrastructure.
• Triage bugs and mentor junior engineers.

What they ask for

• Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
• 8+ years of design verification experience using System Verilog and UVM.
• 8+ years of testbench development, including stimulus, checkers, assertions, and coverage.

Nice to have

• Experience with verification platforms, design levels, C/C++, scripting languages such as Python, AMBA and interconnect protocols, memory subsystems, or complex CPU, GPU, or ML accelerator designs.

Pay

USD 213,000.00 - 287,500.00 annually base salary; USD 185,200.00 - 250,000.00 annually base salary

Tools

System Verilog, UVM, FPGA, C/C++, Python, AMBA, AHB/APB/AXI, PCIe and UCIe

AI focus

The team develops Inferentia and Trainium SoCs for AI workloads; this role verifies custom machine-learning accelerator chip designs.