Amazon
Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
$185K–$288K
Tempe, AZ +3 · Senior · Full-time · Posted Jul 5, 2026
- Location
- Tempe, AZ
Austin, TX
Portland, OR
Cupertino, CA - Experience
- 10+ years required; preferred qualifications also state 7+ years in IC package layout and physical design.
- Education
- Bachelor's degree in Electrical Engineering or a related field; preferred Master's degree or equivalent in mechanical engineering, electrical engineering, material science, physics or equivalent.
About the job
Leads end-to-end physical design of advanced IC packages for next-generation machine-learning and data-center ASICs, from floor planning through tape-out and manufacturing release.
What you'll do
- Own package layout, routing, verification, and tape-out across advanced multi-die packaging architectures.
- Optimize package and cross-level layouts for power delivery, high-speed signaling, manufacturability, and reliability; coordinate with engineering teams and manufacturing partners.
- Manage schedules and design closure, and mentor junior layout engineers.
What they ask for
- Bachelor's degree in Electrical Engineering or a related field.
- 10+ years of experience in IC package layout and physical design.
- Track record leading complex, multilayer organic substrate or silicon interposer designs from concept through tape-out.
- Hands-on expertise with package layout tools; knowledge of advanced packaging, design rules, DFM, physical verification, bump maps, routing, and manufacturing processes.
Nice to have
- Experience with chiplet-based or heterogeneous integration packaging architectures.
- Automation scripting experience (Python, TCL, Skill, Ravel) or direct OSAT NPI and yield-improvement experience.
Pay
185,200.00 - 250,000.00 USD annually (base salary); 213,000.00 - 287,500.00 USD annually (base salary); 185,200.00 - 250,000.00 USD annually (base salary); 185,200.00 - 250,000.00 USD annually (base salary)
Tools
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel, CoWoS
AI focus
Physical design of advanced IC packages for next-generation machine-learning ASICs.
Model-written summary · the original posting is authoritative