Amazon
Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
$185K–$288K
Austin, TX +2 · Senior · Full-time · Posted Oct 20, 2026
- Location
- Austin, TX
San Diego, CA
Cupertino, CA - Experience
- 7+ years of ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller).
- Education
- Bachelor's degree in Electrical Engineering or a related field.
About the job
Develops and deploys physical design and signoff methodologies for machine-learning accelerator chips, optimizing design quality, performance, and engineering workflows.
What you'll do
- Develop STA/EMIR signoff and RTL2GDS methodologies and optimize CAD flows for PPA and turnaround time.
- Evaluate EDA tools with vendors, troubleshoot flows, and improve cloud compute and storage utilization.
- Build scalable scripts, dashboards, and reports; coordinate methodology improvements with design and test teams.
What they ask for
- Bachelor's degree in Electrical Engineering or a related field.
- Knowledge of multiple power islands and power gating, and experience with low-power design techniques.
- Experience leading or independently developing physical synthesis methodologies and scripts.
- Experience leading technical initiatives and key deliverables, and with version control systems and CI/CD pipeline implementation.
Nice to have
- Master's or Ph.D. degree in Electrical Engineering or a related field.
- Experience in RTL coding and debug, and performance, power, and area analysis and trade-offs.
Pay
213,000.00 - 287,500.00 USD annually (base salary); 185,200.00 - 250,000.00 USD annually (base salary)
Tools
ASIC, STA, EMIR, RTL2GDS, TCL, Python, CI/CD
AI focus
Develops and optimizes physical design methodologies for machine-learning accelerator chips, including AWS Inferentia and Trainium systems.
Model-written summary · the original posting is authoritative