Amazon
Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
$185K–$288K
Austin, TX +2 · Senior · Full-time · Posted Oct 20, 2026
- Location
- Austin, TX
San Diego, CA
Cupertino, CA - Experience
- 7+ years of ASIC implementation, synthesis, STA, and physical design experience in deep sub-micron nodes (16nm or smaller).
- Education
- Bachelor's degree in Electrical Engineering or a related field.
About the job
Develops and deploys physical design and verification methodologies and tools for machine-learning accelerator chips, improving design quality, performance, and workflow efficiency.
What you'll do
- Develop RTL-to-GDS physical design and verification methodologies, and optimize CAD flows for PPA and turnaround time.
- Evaluate EDA methods with vendors, troubleshoot tool flows, and improve cloud compute and storage utilization.
- Collaborate across design teams; build scalable scripts and project dashboards for tracking quality-of-results and statistics.
What they ask for
- Bachelor's degree in Electrical Engineering or a related field.
- Experience with ASIC implementation, synthesis, STA, and physical design in deep sub-micron nodes (16nm or smaller).
- Knowledge of multiple power islands, power gating, and low-power design techniques.
- Experience developing physical synthesis methodology and scripts, leading technical initiatives, and implementing version control systems and CI/CD pipelines.
Nice to have
- Master's or Ph.D. in Electrical Engineering or a related field.
- Experience in RTL coding and debugging, and performance, power, and area analysis and trade-offs.
Pay
USD 213,000.00 - 287,500.00 annually (base salary); USD 185,200.00 - 250,000.00 annually (base salary)
Tools
ASIC, RTL2GDS, TCL, Python, EDA, STA, CI/CD
AI focus
Develops physical design methodologies for machine-learning accelerator chips, including AWS Inferentia and Trainium systems.
Model-written summary · the original posting is authoritative