Amazon
Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
$213K–$288K
San Diego, CA +1 · Senior · Full-time · Posted Oct 8, 2026
- Location
- San Diego, CA
Cupertino, CA - Experience
- BS + 8 years or MS + 6 years or PhD + 4 years; also requires 3+ years doing Static Timing Analysis and 3+ years with timing constraint development.
- Education
- BS, MS, or PhD in EE/CS.
About the job
Develop and optimize static timing analysis flows and constraints for block- and full-chip designs supporting AWS cloud-scale machine-learning hardware.
What you'll do
- Develop and maintain block- and full-chip static timing analysis flows, constraints, and automated scripts and reports.
- Run timing analysis, provide feedback, and advise on fixing timing issues, including ECOs and constraint problems.
- Collaborate with physical design, RTL, and architecture teams.
What they ask for
- Experience in one or more scripting languages, such as Python, Ruby, or Perl.
- Expertise in timing analysis fundamentals and at least 3 years doing Static Timing Analysis and developing timing constraints.
- Timing analysis using EDA tools; understanding of ASIC physical design from RTL-to-GDSII and other sign-off activities (ir/em, physical verification, DFT).
- EE/CS degree and experience: BS + 8 years, MS + 6 years, or PhD + 4 years.
Nice to have
- Experience mentoring, leading, and coaching; developing STA flows or ECO flows.
- Experience with advanced nodes (16nm or below), parasitic extraction, circuit-level analysis, or timing of IO interfaces.
Pay
213,000.00 - 287,500.00 USD annually (base salary)
Tools
Python, Ruby, Perl, PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker
AI focus
Supports design and optimization of hardware for cloud-scale machine-learning acceleration, including AWS Inferentia, a machine-learning inference product.
Model-written summary · the original posting is authoritative