Anthropic
Research Engineer, Chip Design RL
$500K–$850K
San Francisco, CA +1 · Full-time · Posted Oct 21, 2026
- Location
- San Francisco, CA
San Francisco, California, United States - Experience
- Years of experience required will correlate with the internal job level requirements for the position; no specific number stated.
- Education
- Bachelor’s degree or an equivalent combination of education, training, and/or experience. Relevant field of study demonstrated through coursework, training, or professional experience.
- Visa sponsorship
- Visa sponsorship is offered, but may not be available for every role or candidate; the company says it will make every reasonable effort to obtain a visa after an offer.
About the job
Develops reinforcement-learning environments and evaluations to train AI agents in chip design, verification, and physical-design optimization, and brings the work into research and production training.
What you'll do
- Design and implement RL environments and evaluations for agentic RTL generation, design verification, and physical-design optimization.
- Explore cross-cutting RL improvements, including EDA-tool latency optimization and proxy rewards; conduct experiments and shape the roadmap.
- Deliver work into research and production training runs and collaborate with researchers and engineers.
What they ask for
- Expertise in ASIC or FPGA design, including relevant design, verification, or physical-design workflows.
- Fluency with industry EDA tools and processes.
- Experience taping out chips and taking designs from specification to silicon.
- Bachelor’s degree or an equivalent combination of education, training, and/or experience; relevant field of study demonstrated through coursework, training, or professional experience.
Nice to have
- Experience with reinforcement learning, evaluations, or environments; chip-design tooling or automation.
- Experience with ML accelerators or high-performance compute hardware; familiarity with high-level synthesis or architecture simulators.
Pay
$500,000 — $850,000 USD annual salary (base salary)
Tools
ASIC, FPGA, RTL, UVM, EDA, DFT, ECOs
AI focus
Uses reinforcement learning to improve AI agents’ chip-design capabilities, including RTL generation, formal verification, and physical-design optimization.
Model-written summary · the original posting is authoritative