Apple
AMS SerDes Robustness Analysis Validation Architect
$185K–$325K
San Francisco Bay Area, California · Full-time · Posted Jan 20, 2026
- Experience
- 10+ years of relevant industry experience; preferred qualification specifies 10+ years in SerDes IP validation, AMS circuit design, or silicon/system-level debug.
- Education
- BS; preferred: PhD in Electrical Engineering or related field.
About the job
Architects and leads hands-on validation of high-speed SerDes PHY robustness, performance, and margins from design through production.
What you'll do
- Define and execute margin-to-fail and stress-to-fail validation across PVT conditions and system environments.
- Lead lab experiments to isolate and root-cause failures, analyze silicon behavior, and refine test coverage.
- Collaborate with design, architecture, system, and validation teams on observability, design-for-test, coverage, and post-silicon feedback.
What they ask for
- BS degree.
- 10+ years of relevant industry experience.
Nice to have
- PhD in Electrical Engineering or a related field, with 10+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug.
- Hands-on SerDes lab instrumentation experience and expertise in serial-link protocols, analog/mixed-signal design, validation automation, and debug.
Pay
$184,700 and $324,800 (base salary range)
Tools
SerDes, PCIe, USB, Ethernet, DisplayPort, CTLE, DFE, FFE
Model-written summary · the original posting is authoritative