Apple
AMS SerDes Robustness Analysis Validation Architect
$262K–$394K
San Francisco Bay Area, California · Full-time · Posted Jan 20, 2026
- Experience
- 20+ years of relevant industry experience; preferred qualification specifies 20+ years in SerDes IP validation, AMS circuit design, or silicon/system-level debug.
- Education
- BS; preferred: PhD in Electrical Engineering or related field.
About the job
Architect and conduct hands-on validation of high-speed SerDes PHYs, finding failure margins and improving robustness from design through production.
What you'll do
- Develop stress-to-fail and margin-to-fail validation strategies across PVT conditions and system environments.
- Run lab experiments, analyze silicon behavior, and root-cause failures across standalone IP and system interactions.
- Collaborate with design and validation teams to improve testability, coverage, and validation efficiency; guide junior engineers.
What they ask for
- BS degree.
- 20+ years of relevant industry experience.
Nice to have
- PhD in Electrical Engineering or a related field, with 20+ years of experience in SerDes IP validation, AMS circuit design, or silicon/system-level debug.
- Hands-on SerDes lab instrumentation experience and knowledge of high-speed protocols, equalization, analog/mixed-signal design, and validation programming.
Pay
$262,500 to $394,000 USD base salary
Tools
SerDes, PCIe, USB, Ethernet, DisplayPort, CTLE, DFE, FFE
Model-written summary · the original posting is authoritative