Apple
ASIC Design and Integration Engineer
$185K–$325K
Beaverton, Oregon +1 · Full-time · Posted Apr 10, 2026
- Location
- Beaverton, Oregon
Cupertino, California - Experience
- Minimum of 10 years of relevant industry experience; preferred qualifications also state 8+ years of ASIC design experience.
- Education
- BS
About the job
Design, verify, and integrate custom ASICs and digital designs for complex SoCs, with a focus on timing and power goals.
What you'll do
- Design, implement, and verify ASICs; develop RTL and perform synthesis.
- Coordinate with verification, hardware, and software teams to validate and integrate designs into SoCs.
- Conduct timing analysis and power optimization, and create micro-architecture and design documentation.
What they ask for
- BS degree and 10 years of relevant industry experience.
- Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
- Hands-on experience with ASIC design tools and methodologies.
- Experience across front-end chip development, such as CDC/RDC, LINT, and LEC.
Nice to have
- Experience with high-speed I/O design and protocols; PCIe knowledge is a plus.
- Familiarity with custom ASIC design, FPGA prototyping, and low-power design techniques.
Pay
$184,700 and $324,800 (base salary range; USD)
Tools
SystemVerilog, PCIe, CDC/RDC, LINT, LEC, FPGA
Model-written summary · the original posting is authoritative