Apple
ASIC Design and Integration Engineer
$129K–$195K
Beaverton, Oregon +1 · Full-time · Posted Aug 10, 2026
- Location
- Beaverton, Oregon
Cupertino, California - Experience
- Minimum of BS +0 years relevant industry experience.
- Education
- BS
About the job
Design and integrate custom ASICs and SoCs, from RTL implementation and verification through timing and power optimization.
What you'll do
- Design ASICs and develop SystemVerilog RTL; perform synthesis.
- Coordinate with verification teams and hardware and software groups to validate and integrate digital designs into SoCs.
- Analyze timing and power, optimize for PPA goals, and document micro-architecture and designs.
What they ask for
- Bachelor of Science degree.
- At least 0 years of relevant industry experience.
Nice to have
- Coursework in ASIC design, including RTL design and verification, and hands-on experience with ASIC design tools and methodologies.
- Knowledge of CDC and RDC.
Pay
$129,300 and $194,700 (base salary)
Tools
SystemVerilog, RTL
Model-written summary · the original posting is authoritative