Apple
ASIC Design and Integration Engineer – Silicon Security
$185K–$325K
Cupertino, California · Full-time · Posted Aug 19, 2026
- Experience
- 10 years of industry experience and 10 years of RTL design experience using Verilog or SystemVerilog.
- Education
- Bachelor’s in Electrical Engineering, Computer Engineering, or a relevant field.
About the job
Designs and integrates secure ASIC subsystems and hardware defenses for Apple SoCs, from micro-architecture and RTL through front-end quality flows.
What you'll do
- Architect and design security features and efficient RTL blocks in collaboration with platform architecture and design verification teams.
- Integrate security IPs, meet timing, performance, and security requirements, and resolve cross-IP integration issues.
- Drive RTL-to-netlist quality flows, including Lint, CDC/RDC analysis, UPF development, timing, and Synthesis; use AI-assisted tools to improve quality and productivity.
What they ask for
- Bachelor’s in Electrical Engineering, Computer Engineering, or a relevant field.
- 10 years of industry experience.
- 10 years of RTL design experience using Verilog or SystemVerilog.
Nice to have
- Experience with CDC/RDC analysis and verification, lint, synthesis, and timing closure; familiarity with AMBA (AXI, AHB, APB) and low-power design techniques.
- Cryptography or cryptographic algorithm implementation background is a bonus.
Pay
$184,700 and $324,800 (USD, base salary)
Tools
Verilog, SystemVerilog, Lint, CDC/RDC, UPF, Synthesis, AMBA (AXI, AHB, APB)
AI focus
Leverage AI-assisted tools to enhance design quality and productivity.
Model-written summary · the original posting is authoritative