Apple
ASIC Design and Integration Engineer – Silicon Security
$129K–$195K
Cupertino, California · Full-time · Posted Aug 4, 2026
- Experience
- 0 years of experience required.
- Education
- BS in Electrical Engineering, Computer Engineering, or a relevant field.
About the job
Designs and integrates secure ASIC subsystems and RTL blocks that protect Apple SoCs and meet performance, power, timing, and security requirements.
What you'll do
- Architect and design security features and efficient RTL blocks in collaboration with architecture and verification teams.
- Integrate security IPs, resolve cross-IP issues, and coordinate interface and functionality concerns with IP owners.
- Drive RTL-to-netlist quality flows, including lint, CDC/RDC analysis, UPF development, timing, synthesis, and AI-assisted design tools.
What they ask for
- BS in Electrical Engineering, Computer Engineering, or a relevant field.
- Verilog or SystemVerilog RTL design experience, including fundamentals such as finite state machines and pipelining.
- Understanding of digital design fundamentals, including CDC, synthesis, and timing closure.
- Familiarity with on-chip bus protocols such as AMBA (AXI, AHB, APB).
Nice to have
- Familiarity with low-power design techniques.
- Background in cryptography and cryptographic algorithm implementations.
Pay
$129,300 and $194,700 (base salary)
Tools
Verilog, SystemVerilog, AMBA, AXI, AHB, APB, UPF
AI focus
Use AI-assisted tools to enhance design quality and productivity.
Model-written summary · the original posting is authoritative