Apple
ASIC Design and Integration Engineer – Silicon Security
$150K–$278K
Cupertino, California · Full-time · Posted Aug 4, 2026
- Experience
- 3 years of industry experience; 3 years of RTL design experience.
- Education
- BS in Electrical Engineering, Computer Engineering, or a relevant field.
About the job
Designs and integrates secure ASIC subsystems and hardware defenses for Apple SoCs, from microarchitecture and RTL through front-end quality flows.
What you'll do
- Architect and design security features and efficient RTL blocks with partner teams.
- Integrate security IPs and resolve cross-IP issues while meeting timing, performance, and security requirements.
- Run front-end quality flows from RTL to netlist, including Lint, CDC/RDC analysis, UPF development, timing, and Synthesis; use AI-assisted tools to improve quality and productivity.
What they ask for
- BS in Electrical Engineering, Computer Engineering, or a relevant field.
- 3 years of industry experience.
- 3 years of RTL design experience using Verilog or SystemVerilog.
Nice to have
- Experience with CDC/RDC analysis, low-power design and UPF, synthesis, timing closure, or design for testability.
- Background in cryptography, hardware security, subsystem clock/reset architecture, or AMBA bus protocols (AXI, AHB, APB).
Pay
USD $150,400 and $277,600 (base salary range)
Tools
Verilog, SystemVerilog, Lint, CDC/RDC, UPF, Synthesis, AXI, AHB
AI focus
Leverage AI-assisted tools to enhance design quality and productivity.
Model-written summary · the original posting is authoritative