Apple
ASIC Design Engineer - Cache Controller
$185K–$325K
Santa Clara, California · Full-time · Posted Apr 10, 2026
- Experience
- 10+ years of full-time ASIC design experience.
- Education
- B.S. in a relevant field.
About the job
Designs and develops cache-subsystem hardware and microarchitecture for high-performance SoCs, including RTL, PPA analysis, and timing closure.
What you'll do
- Define cache microarchitecture and assess architecture trade-offs in performance, area, and power.
- Develop and debug RTL, and perform front-end netlist and area/timing analysis.
- Work with the physical design team on cache-subsystem timing closure.
What they ask for
- ASIC design experience in memory system development, RTL/microarchitecture definition, and PPA analysis.
- Cache design background, including memory organizations and trade-offs.
- Hands-on experience with multiprocessor cache coherence protocols.
- B.S. in a relevant field.
Nice to have
- Knowledge of high-performance coherent memory systems or interconnect architectures.
- Knowledge of high-performance DRAM controller; M.S. in a relevant field.
Pay
USD $184,700 to $324,800 base salary
Tools
ASIC, SoC, RTL
Model-written summary · the original posting is authoritative