Apple
ASIC Design Engineer - Cache Controller
$150K–$278K
Santa Clara, California · Full-time · Posted Apr 10, 2026
- Experience
- 3+ years of full-time ASIC design experience.
- Education
- B.S. in a relevant field.
About the job
Designs and develops cache-subsystem hardware for high-performance SoCs, from microarchitecture and RTL through analysis and timing closure.
What you'll do
- Develop cache microarchitecture and evaluate performance, area, and power trade-offs.
- Design and debug RTL for cache-subsystem components; conduct netlist, area, and timing analysis.
- Collaborate with physical design on cache-subsystem timing closure.
What they ask for
- Memory system development experience.
- RTL/microarchitecture definition experience.
- PPA (performance/power/area) analysis experience.
- B.S. in a relevant field.
Nice to have
- Cache design knowledge, including memory organizations and trade-offs; experience with multiprocessor cache coherence protocols.
- Knowledge of high-performance coherent memory systems or interconnect architectures, or high-performance DRAM controllers; M.S. in a relevant field.
Pay
$150,400 to $277,600 USD base salary
Tools
ASIC, RTL, SoC, PPA
Model-written summary · the original posting is authoritative