Apple
ASIC Design Engineer - Cache Controller
$129K–$195K
Santa Clara, California · Full-time · Posted Jul 29, 2026
- Experience
- B.S. in a relevant field plus 0 years of industry experience.
- Education
- B.S. in a relevant field.
About the job
Designs and develops cache-subsystem hardware and micro-architecture for high-performance SoCs, analyzing performance, area, and power and supporting timing closure.
What you'll do
- Develop cache micro-architecture and RTL designs.
- Analyze architectural trade-offs, netlists, area, and timing.
- Collaborate with physical design on cache-subsystem timing closure.
What they ask for
- In-depth knowledge of memory subsystems.
- Academic experience with RTL and micro-architecture development.
- Good understanding of performance/power/area trade-offs.
- B.S. in a relevant field.
Nice to have
- Cache design experience and knowledge of memory organizations and trade-offs.
- Experience with cache coherence protocols or knowledge of coherent memory systems, interconnect architectures, or DRAM controllers; M.S. in a relevant field.
Pay
USD $129,300–$194,700 base salary
Tools
RTL, SoC
Model-written summary · the original posting is authoritative