Apple
ASIC Design Engineer – Fabric/Interconnect
$185K–$325K
Austin, Texas +1 · Full-time · Posted Jan 15, 2026
- Location
- Austin, Texas
Santa Clara, California - Experience
- Minimum of 10 years of relevant industry experience.
- Education
- BS
About the job
Design and integrate coherent and non-coherent interconnect fabrics for subsystems or SoCs, delivering high-quality RTL and coordinating with cross-functional teams.
What you'll do
- Design and integrate interconnect fabrics; develop RTL, templates, scripts, and RTL generation.
- Integrate shared IP and optimize memories and hard macros; work with synthesis and STA teams to meet timing.
- Coordinate with verification, power/performance, and other teams to deliver designs on schedule and with quality checks.
What they ask for
- Knowledge of interconnect fabrics and system memory hierarchy.
- Minimum BS degree.
- 10 years of relevant industry experience.
Nice to have
- Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy; track record delivering large, sophisticated, high-volume designs for low-power applications.
- Experience working with synthesis, power, performance, and verification teams; familiarity with front-end tools including lint, CDC, synthesis.
Pay
USD $184,700 to $324,800 base salary
Tools
RTL, NoC, crossbars, MESI, MOESI, lint, CDC, synthesis
Model-written summary · the original posting is authoritative