Apple
ASIC Design Engineer – Fabric/Interconnect
$150K–$278K
Austin, Texas +1 · Full-time · Posted Apr 10, 2026
- Location
- Austin, Texas
Santa Clara, California - Experience
- Minimum of 3 years of relevant industry experience.
- Education
- BS
About the job
Designs and integrates coherent and non-coherent interconnect fabrics for subsystems or SoCs, delivering high-quality RTL that meets timing and schedule requirements.
What you'll do
- Design and integrate fabric architectures, and develop RTL, templates, scripts, and RTL generation.
- Integrate shared IP and optimize memories or hard macros; coordinate with synthesis, STA, power/performance, and verification teams.
- Collaborate across groups to deliver designs on schedule with quality checks throughout the design process.
What they ask for
- Bachelor of Science degree.
- Relevant industry experience.
- Knowledge of interconnect fabrics and system memory hierarchy.
Nice to have
- Knowledge of cache coherency protocols such as MESI, MOESI, and directory-based coherence.
- Experience delivering large designs for low-power, high-volume production; familiarity with front-end tools including lint, CDC, and synthesis.
Pay
$150,400 to $277,600 USD base salary
Tools
RTL, NoC topologies, crossbars, arbitration, MESI, MOESI, lint, CDC
Model-written summary · the original posting is authoritative