Apple
ASIC Design Engineer – Fabric/Interconnect
$129K–$195K
Austin, Texas +1 · Full-time · Posted Oct 12, 2026
- Location
- Austin, Texas
Santa Clara, California - Experience
- Minimum of 0 years relevant industry experience.
- Education
- BS
About the job
Designs and integrates coherent and non-coherent on-chip interconnect fabrics for subsystems and SoCs, delivering high-quality RTL on schedule.
What you'll do
- Develop, template, script, and generate RTL; integrate fabric designs and shared IP into blocks or SoCs.
- Collaborate with synthesis/STA, power/performance, verification, and other teams to meet timing and quality goals.
- Integrate shared IP and optimize memories and hard macros required for the block.
What they ask for
- Knowledge of interconnect fabrics and system memory hierarchy.
- Bachelor of Science degree or higher.
Nice to have
- Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
- Familiarity with front-end tools including lint, CDC, and synthesis.
Pay
$129,300 to $194,700 USD base salary
Tools
RTL, NoC, crossbars, MESI, MOESI, lint, CDC, synthesis
Model-written summary · the original posting is authoritative