Apple
ASIC Design Engineer — Neural Engine DMA
$185K–$325K
Sunnyvale, California · Full-time · Posted Jul 8, 2026
- Experience
- 10 years of industry experience.
- Education
- Bachelor’s degree.
About the job
Design and take end-to-end ownership of Neural Engine DMA subsystems, from microarchitecture specification and RTL implementation through front-end signoff and verification closure.
What you'll do
- Own DMA subsystem design through specification, RTL implementation, front-end signoff, and design verification closure.
- Write parameterized RTL, assertions, and cover points; collaborate on architectural trade-offs and performance, power, and area targets.
- Work with design, verification, formal verification, architecture, and physical implementation teams to confirm functional correctness and debug issues.
What they ask for
- Bachelor’s degree.
- 10 years of industry experience.
Nice to have
- Experience designing SoC front-end RTL in Verilog or SystemVerilog through multiple tapeouts, including synthesis, timing closure, area and power analysis, linting, and logic equivalence checks.
- Experience with DMA microarchitecture, on-chip bus protocols or interconnects, high-bandwidth domains, micro-architectural specifications, or scripting languages such as Python, Perl, or Tcl.
Pay
$184,700 and $324,800 USD base salary
Tools
Verilog, SystemVerilog, AMBA AXI, AHB, APB, Python, Perl, Tcl
AI focus
Design DMA engines that move model weights and activation tensors between the memory subsystem and the Apple Neural Engine.
Model-written summary · the original posting is authoritative