Apple
ASIC Design Engineer — Pixel IP
$150K–$278K
Sunnyvale, California · Full-time · Posted Aug 28, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- Bachelor’s Degree in EE/CE.
About the job
Design and optimize high-performance, low-power pixel-processing ASICs for capturing, improving, compressing, decompressing, and displaying images and video.
What you'll do
- Design digital hardware using RTL or high-level synthesis, including assertions and cover points, and write micro-architectural specifications.
- Collaborate across architecture, design, and verification teams to balance performance, power, and area.
- Synthesize and optimize designs, then work with verification teams to debug and verify functionality and performance.
What they ask for
- Bachelor’s Degree in EE/CE.
- 3+ years of relevant industry experience.
Nice to have
- SoC front-end ASIC RTL digital logic design experience using Verilog or System Verilog; media, video, pixel, or display design experience.
- Experience with front-end implementation, low-power design, on-chip bus protocols, ASIC/FPGA methodologies, or scripting languages.
Pay
$150,400 to $277,600 USD base salary
Tools
RTL, Verilog, System Verilog, AMBA (AXI, AHB, APB), Python, Perl, TCL
Model-written summary · the original posting is authoritative