Apple
ASIC Design Engineer — Pixel IP
$129K–$195K
Sunnyvale, California · Full-time · Posted Aug 28, 2026
- Education
- Bachelor’s Degree in EE/CE.
About the job
Design and optimize high-performance, low-power ASIC pixel-processing pipelines for capturing, improving, compressing, decompressing, and displaying images and video.
What you'll do
- Write RTL and detailed micro-architectural specifications, including embedded assertions and cover points.
- Collaborate across architecture, design, and verification teams to balance performance, power, and area.
- Synthesize and optimize designs, and work with verification teams to debug and verify functionality and performance.
What they ask for
- Bachelor’s Degree in EE/CE.
Nice to have
- Front-end ASIC RTL design using Verilog or System Verilog; computer-architecture fundamentals such as finite state machines, pipelining, and parallelism.
- Familiarity with AMBA protocols, synthesis and PPA analysis, scripting languages, High-Level Synthesis, SystemC/C++, or digital signal processing.
Pay
$129,300 and $194,700 USD base salary
Tools
RTL, Verilog, System Verilog, AMBA, AXI, AHB, APB, Python
Model-written summary · the original posting is authoritative