Apple
ASIC Design Engineer - Pixel IP ANE
$185K–$325K
Sunnyvale, California · Full-time · Posted Sep 1, 2026
- Experience
- 10 years of experience with a BS.
- Education
- BS
About the job
Design and integrate pixel IP for Apple’s next-generation Neural Engine, developing high-performance RTL and coordinating verification, synthesis, timing, clock-domain, and test work.
What you'll do
- Design RTL for high-speed, high-performance subsystems.
- Work with verification teams and physical design and static timing teams to verify designs and produce high-quality netlists through synthesis.
- Analyze clock-domain crossings and coordinate with DFT and BIST teams to ensure designs are testable.
What they ask for
- BS degree.
- Extensive knowledge of computer architecture, including bus topologies and protocols such as AMBA.
Nice to have
- Experience with large, high-speed compute systems, clock-domain-crossing designs, synthesis, static timing analysis, or power intent.
Pay
$184,700 and $324,800 USD base salary
Tools
RTL, AMBA, Synthesis, Static Timing Analysis, Power Intent, DFT, BIST
AI focus
Designs pixel IP for the next-generation Apple Neural Engine, contributing to AI/ML hardware.
Model-written summary · the original posting is authoritative