Apple
ASIC Design Engineer - Pixel IP ANE
$150K–$278K
Sunnyvale, California · Full-time · Posted Sep 1, 2026
- Experience
- BS + 3 years of experience
- Education
- BS
About the job
Design and integrate pixel IP for Apple’s next-generation Apple Neural Engine, including RTL design, verification, synthesis, and timing work.
What you'll do
- Design high-speed, high-performance subsystems in RTL.
- Collaborate with verification, physical design, static timing, DFT, and BIST teams to verify, synthesize, and test designs.
- Analyze clock-domain crossings for correctness.
What they ask for
- BS degree.
- Extensive knowledge of computer architecture, including bus topologies and protocols such as AMBA.
Nice to have
- Experience with large, high-speed compute systems, clock-domain crossing designs, synthesis, static timing analysis, or power intent.
Pay
$150,400 and $277,600 USD base salary
Tools
RTL, AMBA, synthesis, Static Timing Analysis, Power Intent, DFT, BIST
AI focus
Design work for the next-generation Apple Neural Engine, contributing to AI/ML product capabilities.
Model-written summary · the original posting is authoritative