ASIC Design Engineer — Pixel IP

What you'll do

• Design digital hardware using RTL or high-level synthesis, including assertions and cover points; write micro-architectural specifications.
• Optimize designs for performance, power, and area through synthesis and collaborate with design and verification teams to debug and verify functionality.
• Manage deliverables and work cross-functionally to support project goals.

What they ask for

• Bachelor’s Degree in EE/CE.
• 10+ years of relevant industry experience.

Nice to have

• SoC front-end ASIC RTL design experience using Verilog and System Verilog; media, video, pixel, or display design experience.
• Experience with low-power design, verification and implementation tasks, on-chip bus protocols, and scripting languages.

Pay

$184,700 and $324,800 USD base salary

Tools

RTL, Verilog, System Verilog, AMBA (AXI, AHB, APB), Python, Perl, TCL