Apple
CAD Engineer – Design Verification Methodology
$166K–$325K
Austin Metro Area, Texas +3 · Full-time · Posted Apr 15, 2026
- Location
- Austin Metro Area, Texas
San Francisco Bay Area, California
Beaverton, Oregon
Waltham, Massachusetts - Experience
- Minimum of 10 years of relevant experience.
- Education
- Minimum of BS degree.
About the job
Develops and supports software regression systems that simulate Apple silicon designs, identify defects, and help ensure chip designs are ready for tape-out.
What you'll do
- Develop, maintain, and enhance systems for regression-testing RTL in software simulation.
- Diagnose vendor-tool problems and work with EDA vendors to adopt tool capabilities and resolve issues.
- Support DV and chip-design engineers by investigating problems and improving regression methods.
What they ask for
- Bachelor of Science degree.
- Relevant experience developing, maintaining, and enhancing an existing RTL regression system.
- Experience debugging vendor tool problems.
- Python programming background.
Nice to have
- Experience with TCL or Perl; artificial intelligence and machine learning; or interacting with DV teams to solve problems.
- MSEE/CE/CS; knowledge of Verilog or SystemVerilog; simulation or emulation tools; or familiarity with Verdi, Indago, C, or C++.
Pay
$165,800 to $292,400 USD base salary; $184,700 to $324,800 USD base salary
Tools
Python, TCL, Perl, Verilog, SystemVerilog, VHDL, VCS, XCelium
AI focus
Artificial intelligence and machine learning experience is preferred; the posting does not specify AI responsibilities.
Model-written summary · the original posting is authoritative