Apple
CAD Engineer – EMIR Signoff
$185K–$278K
Austin, Texas +1 · Full-time · Posted Oct 5, 2026
- Location
- Austin, Texas
Sunnyvale, California - Experience
- 3+ years of relevant industry experience.
- Education
- BS
About the job
Develop and support EMIR signoff methodologies and flows for complex mixed-signal SoC designs, ensuring verification and analysis are completed before tapeout.
What you'll do
- Develop, define, and refine gate- and transistor-level signoff methodologies for IR, EM, scan-mode IVD, package models, power switches, and IP reuse.
- Define signoff requirements and work with Design, CAD, and Technology teams to configure and verify EDA flows and tools.
- Support design groups with flow enablement, enhancements, and debugging; explore AI/ML and LLM techniques for signoff automation and analysis.
What they ask for
- Bachelor’s degree and 3+ years of relevant industry experience.
- Experience in CAD, EMIR analysis, or related circuit design roles.
Nice to have
- Knowledge of Redhawk, Voltus, and Totem; Perl and Python proficiency.
- Experience with simulation and power analysis, CMOS analog/mixed-signal design, or AI/ML and LLM-based EDA automation.
Pay
$184,700 and $277,600 (USD, base salary range)
Tools
Redhawk, Voltus, Totem, Perl, Python
AI focus
Explore AI/ML and LLM-driven techniques to accelerate analysis, automate flow debugging, and surface anomalies earlier in the design cycle.
Model-written summary · the original posting is authoritative