Apple
CAD Engineer - Timing for Gate-Level Flows & Methodologies
$150K–$278K
Austin, Texas +1 · Full-time · Posted Apr 13, 2026
- Location
- Austin, Texas
San Jose, California - Experience
- 3 years of relevant industry experience.
- Education
- BS
About the job
Develops and improves static timing analysis (STA) flows and methodologies for Apple Silicon designs, supporting timing analysis, closure, and performance improvement.
What you'll do
- Develop, maintain, and enhance gate-level STA flows, scripts, and timing-analysis methods.
- Work with design teams to debug constraints, flow scripts, and timing-closure issues, including post-silicon timing debug.
- Drive STA methodology improvements and collaborate with EDA vendors on capabilities and technical problems.
What they ask for
- BS degree.
- 3 years of relevant industry experience.
Nice to have
- Experience with static timing analysis tools and flows, including large high-performance SoC designs in deep sub-micron technologies.
- Programming fundamentals; familiarity with Python and Tcl or other high-level languages, and knowledge of noise, cross-talk, variation, timing margins, and timing/SDC constraints.
Pay
$150,400 and $277,600 (base salary range)
Tools
Python, Tcl, STA, SDC
Model-written summary · the original posting is authoritative