Apple
CPU Cache Microarchitect/RTL Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Oct 29, 2025
- Experience
- 3+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Drives CPU multi-level cache subsystem architecture and RTL development for multiprocessor systems, from architectural exploration through design delivery and verification.
What you'll do
- Develop microarchitecture and detailed specifications for CPU cache subsystems.
- Own and refine RTL to meet power, performance, area, and timing goals; support functional verification.
- Explore performance strategies and collaborate on physical design implementation and verification.
What they ask for
- Experience with microprocessor architecture and logic design principles, including timing and power implications.
- Experience in Verilog or VHDL.
- Experience with simulators and waveform debugging.
- Minimum BS.
Nice to have
- Expertise in cache-related areas such as coherence protocols, interconnects, memory subsystem scheduling, SRAM, prefetchers, or replacement policies.
- Understanding of low-power or high-performance CPU microarchitecture techniques; experience with C/C++, Perl, or Python.
Pay
USD $150,400 to $277,600 base salary
Tools
Verilog, VHDL, C, C++, Perl, Python
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