Apple
CPU Cache Microarchitect/RTL Engineer
$166K–$325K
Beaverton, Oregon +2 · Full-time · Posted Oct 29, 2025
- Location
- Beaverton, Oregon
Santa Clara, California
Waltham, Massachusetts - Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Develops CPU multi-level cache architecture and RTL for multiprocessor systems, from specification through verification and design delivery.
What you'll do
- Develop and specify cache microarchitecture, from architectural exploration to detailed specifications.
- Own and refine RTL to meet power, performance, area, and timing goals; support verification and performance correlation.
- Work with cross-functional teams to implement and verify physical design for timing, area, reliability, testability, and power.
What they ask for
- Bachelor’s degree (BS) and 10+ years of relevant industry experience.
- Experience with microprocessor architecture and logic design principles, including timing and power implications.
- Experience with Verilog or VHDL.
- Experience with simulators and waveform debugging.
Nice to have
- Expertise in cache-related areas such as coherence protocols, memory queuing, prefetchers, replacement policies, or SRAM design.
- Understanding of low-power or high-performance CPU microarchitecture; experience with C or C++, Perl, or Python.
Pay
USD $184,700 to $324,800 base salary; USD $165,800 to $292,400 base salary
Tools
Verilog, VHDL, C, C++, Perl, Python
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