Apple
CPU Cache Microarchitect/RTL Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Apr 13, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Develop CPU multi-level cache architecture and RTL for multiprocessor systems, supporting verification, performance analysis, and physical design delivery.
What you'll do
- Develop cache microarchitecture and detailed specifications.
- Own and refine RTL to meet power, performance, area, and timing goals; support verification.
- Explore performance strategies and collaborate on physical design implementation and verification.
What they ask for
- Bachelor’s degree minimum and 3+ years of relevant industry experience.
- Experience with microprocessor architecture and logic design principles, including timing and power implications.
- Experience in Verilog or VHDL.
- Experience with simulators and waveform debugging.
Nice to have
- Expertise in cache-related areas such as coherence, interconnects, memory queuing, SRAM, prefetching, replacement policies, DFT, or error detection and correction.
- Understanding of low-power and high-performance CPU microarchitecture techniques; experience in C or C++ and Perl or Python.
Pay
USD $150,400 to USD $277,600 base salary
Tools
Verilog, VHDL, C, C++, Perl, Python
Model-written summary · the original posting is authoritative