Apple
CPU Cache Microarchitect/RTL Engineer
$166K–$325K
Beaverton, Oregon +2 · Full-time · Posted Apr 13, 2026
- Location
- Beaverton, Oregon
Santa Clara, California
Waltham, Massachusetts - Experience
- 10+ years of relevant industry experience.
- Education
- BS minimum.
About the job
Develops CPU multi-level cache architecture and RTL for multiprocessor systems, from architectural exploration and specification through verification and design delivery.
What you'll do
- Develop and specify microarchitecture, from early exploration through detailed specification.
- Own, assess, and refine RTL to meet power, performance, area, and timing goals; support verification and performance correlation.
- Collaborate with engineering teams on physical design implementation and verification, including timing, area, reliability, testability, and power.
What they ask for
- BS degree and relevant industry experience.
- Experience with microprocessor architecture.
- Experience with logic design principles and their timing and power implications.
- Experience with Verilog or VHDL, simulators, and waveform debugging.
Nice to have
- Expertise in cache-related areas such as coherence protocols, interconnects, memory subsystem queuing, SRAM, prefetchers, or replacement policies.
- Understanding of low-power and high-performance CPU microarchitecture techniques; experience with C or C++ and Perl or Python.
Pay
$184,700 and $324,800 (USD base salary); $165,800 and $292,400 (USD base salary)
Tools
Verilog, VHDL, C, C++, Perl, Python
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