Apple
CPU CDC/RDC/STA Engineer
$185K–$325K
Beaverton, Oregon +1 · Full-time · Posted Apr 14, 2026
- Location
- Beaverton, Oregon
Santa Clara, California - Experience
- 10+ years of relevant industry experience.
- Education
- BS
About the job
Develops and maintains CDC, RDC, and STA constraints, sign-offs, and methodologies for CPU designs, while analyzing issues and coordinating fixes with design teams.
What you'll do
- Develop, improve, and maintain CDC/RDC sign-offs and STA checks for CPU designs.
- Identify CDC/RDC issues, recommend solutions, and work with RTL, DV, CAD, Physical Design, and EDA vendor teams.
- Debug vendor tool problems and recommend System Verilog assertions to support constraints and assumptions.
What they ask for
- BS degree and 10+ years of relevant industry experience.
- Experience with Clock-Domain Crossing (CDC) and Reset Domain Crossing (RDC).
- Experience with at least one of the following: Synopsys or Real Intent tool.
- Scripting experience in TCL or Perl, and experience in Verilog.
Nice to have
- Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations.
- Experience in multi-clock-domain RTL design; knowledge of Spyglass, VC-Static, PrimeTime, or Meridian.
Pay
USD $184,700 to $324,800 base salary
Tools
Synopsys, Real Intent, TCL, Perl, Verilog, SystemVerilog Assertions (SVA), Spyglass, PrimeTime
Model-written summary · the original posting is authoritative