Apple
CPU CDC/STA Engineer
$129K–$195K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Education
- Minimum BS
About the job
Analyzes CPU designs and develops, maintains, and improves CDC, RDC, STA, and lint constraints, sign-offs, and methodology.
What you'll do
- Develop and maintain CDC/RDC and STA sign-offs and checks for CPU designs.
- Work with RTL and DV teams on SystemVerilog assertions supporting CDC/RDC/STA constraints and assumptions.
- Debug vendor-tool problems and collaborate with design teams and EDA vendors on solutions and methodology improvements.
What they ask for
- Minimum BS.
- Scripting experience with TCL or Perl.
Nice to have
- Experience with STA, CDC, or RDC solutions; SystemVerilog Assertions (SVA) and Design Verification (DV) simulations; or Verilog.
- Knowledge of Spyglass, VC-Static, PrimeTime, or Meridian.
Pay
$129,300 to $194,700 USD base salary
Tools
TCL, Perl, System Verilog, Spyglass, VC-Static, PrimeTime, Meridian, Verilog
Model-written summary · the original posting is authoritative