Apple
CPU CDC/STA Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- BS
About the job
Develops and maintains CPU design CDC/RDC and STA constraints, checks, sign-offs, and methodologies, while analyzing designs and coordinating fixes across teams.
What you'll do
- Develop, improve, and maintain CDC/RDC and STA checks and sign-offs for CPU designs.
- Work with RTL and DV teams on SystemVerilog assertions supporting CDC/RDC/STA constraints and assumptions.
- Debug vendor tool problems and collaborate with designers, EDA vendors, and cross-functional teams to resolve issues and improve methodologies.
What they ask for
- BS degree.
- 3+ years of relevant industry experience.
- Scripting experience with TCL or Perl.
- Experience in at least one of STA, CDC, or RDC solutions.
Nice to have
- Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations; experience in Verilog.
- Knowledge of Spyglass, VC-Static, PrimeTime, or Meridian.
Pay
USD 150,400 to USD 277,600 base salary
Tools
TCL, Perl, SystemVerilog, Spyglass, VC-Static, PrimeTime, Meridian, Verilog
Model-written summary · the original posting is authoritative