Apple
CPU Design Timing Engineer
$185K–$325K
Beaverton, Oregon +1 · Full-time · Posted Apr 14, 2026
- Location
- Beaverton, Oregon
Santa Clara, California - Experience
- 10+ years of relevant experience.
- Education
- Minimum BS.
About the job
Leads CPU project timing analysis and closure, developing timing flows and coordinating with CAD, RTL, microarchitecture, and implementation teams.
What you'll do
- Develop timing flows with the CAD team, including scripts to improve analysis and engineering efficiency.
- Work with CPU micro-architects and implementation engineers to drive timing closure.
- Analyze timing and collaborate with implementation and RTL teams on timing changes and closure.
What they ask for
- Experience with a static timing analysis tool such as PrimeTime® or Tempus®.
- Experience with timing analysis across multiple clock and power domains, noise analysis and noise fixes, and variation modeling.
- Experience with TCL and either Perl or Python.
- Experience with SDC commands, including clock definitions, timing exceptions, and IO constraints.
Nice to have
- Timing analysis experience in high-speed digital designs such as CPUs; understanding of physical design tools and methodology, deep sub-micron technologies, CPU microarchitecture, and clock/reset-domain crossing.
- Experience with RTL modeling and assertion-based verification; data parsing, analysis, and plotting skills.
Pay
$184,700 to $324,800 USD base salary
Tools
PrimeTime®, Tempus®, TCL, Perl, Python, SDC
Model-written summary · the original posting is authoritative