Apple
CPU Design Timing Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Experience
- 3+ years of relevant experience.
- Education
- Minimum BS.
About the job
Own CPU project timing closure by developing timing flows, analyzing timing and noise, and coordinating changes with RTL, implementation, CAD, and microarchitecture teams.
What you'll do
- Develop timing flows with the CAD team, including scripts to improve analysis and engineering efficiency.
- Work with CPU micro-architects and implementation engineers to drive timing closure.
- Perform timing analysis and support timing changes, flow construction or modification, and noise fixing.
What they ask for
- Minimum BS degree.
- Experience with static timing analysis, noise analysis, and fixing noise in designs.
- Experience with variation modeling.
- Experience with TCL and either Perl or Python.
Nice to have
- Prior timing analysis experience in high-speed digital designs such as CPUs.
- Experience with PrimeTime®/Tempus® or knowledge of physical design tools and methodology.
Pay
USD 150,400–277,600 base salary
Tools
TCL, Perl, Python, PrimeTime®, Tempus®
Model-written summary · the original posting is authoritative