Apple
CPU Gate Level Synthesis Engineer
$129K–$195K
Santa Clara, California · Full-time · Posted Aug 19, 2026
- Experience
- Experience in at least one of digital logic design, RTL synthesis, or physical design; no duration stated.
- Education
- Minimum BS required.
About the job
Develops and optimizes CPU synthesis flows and designs to improve performance, power, and area, collaborating across RTL, physical design, DFT, and timing teams.
What you'll do
- Assess RTL health and address timing, gate-depth, power, and area issues with design teams.
- Improve synthesis-flow correlation to post-route and analyze PPA trends throughout the project.
- Integrate DFT and support scan chain, ATPG, MBIST, and top-level constraint generation.
What they ask for
- BS degree.
- Experience in at least one of: digital logic design, RTL synthesis, or physical design.
Nice to have
- CPU implementation experience.
- Scripting proficiency in TCL, Perl, or Python for automation and flow optimization.
Pay
$129,300 to $194,700 USD (base salary)
Tools
RTL, TCL, Perl, Python, ATPG, MBIST
Model-written summary · the original posting is authoritative